In interface circuits (transceivers) which are used to couple synchronous communication lines to data communication systems, it is the established practice to provide a circuit which examines the received data bits sequentially and searches, or examines, those bits for one or more occurrences of a particular character, referred to as the "SYNC" character. If, for instance, the characters of such a system were composed of eight bits, then the system would be looking for a certain combination of eight bits (a particular arrangement of ONE's and ZERO's) which represents the SYNC character. When the circuitry recognizes such a character, or in some implementations, a pair of such characters, the transceiver is considered to be "in synchronization." Such an "in synchronization" transceiver generates a "receiver active" or "synchronization achieved" signal. Thereafter the transceiver assembles subsequent eight bit sequences as characters and produces a "character ready" flag each time that such an eight bit sequence has been assembled. It has become the practice to use a plurality of terminals in a data communication system and in order to accommodate such a plurality of terminals, it has become the practice to use a "synchronous multiplexer." In a synchronous multiplexer arrangement, it is desirable to have a first-in, first-out (FIFO) buffer into which received characters are stored before being transferred to the data processor within the data communications system.
When data is being received, there is always a concern as to whether or not the bits received, as an eight bit segment, really constitute a character, or, in fact, constitute portions of two charaters. Accordingly, it is common practice to have some form of error checking test, ("cyclic redundancy check"), within the program of the data processor which is used in the data communication system. To say it another way, periodically within a received message, there are characters whose numerical value is the result of a known mathematical function applied to the other characters in the message and which are deliberately placed in the message, usually at the end, by the transmitting device and those characters are examined by the receiving data processor. If, in fact, those characters do not appear in their prearranged form, then the data processor assumes that the message has been subjected to errors, or, if this condition occurs frequently that the message is being sent "out of synchronization" and the data processor is programmed to do something about it. In such circumstances, the programmer has arranged for the data processor to request that the transceiver circuit re-enter the operating mode in which it examined the receiving bits looking for SYNC characters and this is a process which is known in the prior art as "SYNC Search."
When a data processor initiates a SYNC search directed to a particular terminal, there may be data words from that terminal which are stored in the FIFO buffer and which arrived therein subsequent to the arrival of the invalid error checking word which caused the data processor to generate the SYNC search signal. If such data words exist in the FIFO, they are considered not valid by the system and the system must provide a method and a technology to discard such data words. It should also be recognized that data words which are received in the FIFO buffer, after synchronization has been achieved, are considered to be valid characters and should be retained. Further, in a synchronous multiplexer, there may exist in the FIFO buffer valid data words which have been received from terminals other than the one upon which a "SYNC Search" is requested.
In the prior art, complex systems have made it possible for the programmer to generate a marker to be entered into the FIFO at the time a SYNC Search is initiated. The prior art systems further use the occurrence of the SYNC Search condition to cause the data procressor to go into a program routine which searches for the marker so that the system can distinguish between data words received before and after the SYNC search commenced. The prior art structures which provide this capability to the programmer, employ a great deal of logic circuitry to accomplish the generation of the marker and to accomplish the search circuitry looking for the marker. In addition, it has very often happened that a programmer, thinking that one marker would be worthwhile but two markers would be even better, employs a program to provide two markers, only to find that the computer circuitry was designed to search for only one marker. In such circumstances the computer acts on the second marker as though it were a valid word. In other words, in this situation, when two markers are generated at the whim of the programmer, the second marker is received as a valid data word and the message is burdened with an irregularity from that point on.
The present system eliminates the need for complex logic circuitry to enable the data communication systems to know that resynchronization is being sought and secondly, that resynchronization has been achieved.